This invention relates to semiconductor devices, and more particularly to the manufacture of VLSI devices having planar surfaces.
In order to manufacture VLSI semiconductor devices such as a 1-Megabit dynamic RAM wherein line resolution is in the range of 2 microns or less, it is preferable that the surface of the semiconductor bar be as smooth and plane as possible, and control of the line width is essential. When the metal conductive strips used for interconnections are as narrow as needed for maximum circuit density, the thinning or discontinuity caused by steps along the surface become major problems. One source of these steps is the thick field oxide used to isolate MOS transistors from one another along the surface. Typically this field oxide is created by thermal oxidation using silicon nitride as a mask, as disclosed in U.S. Pat. No. 4,055,444 issued to G. R. Mohan Rao, assigned to Texas Instruments. While this process has been widely used in making hundreds of millions of memory and microcomputer devices, improvements in surface planarity are preferrable in future VLSI products. A method previously used to produce planar surfaces in manufacture of MOS integrated circuits is that of performing a deep etch prior to growth of field oxide so that the top of the field oxide is level with the original suface. One example of this method is shown in U.S. Pat. No. 4,016,594. A problem with this prior method, however, is the growth of thermal oxide beneath the edges of the silicon nitride oxidation mask. This condition, referred to as moat encroachment, is detrimental to the geometric integrity, especially when line widths are in the range of about two microns as needed for high density devices.
It is the principal object of this invention to provide improved processes for making very large scale integrated circuits, particularly for improving surface planarity in such devices and reducing the geometric effects of moat encroachment. Another object is to provide improved step coverage for interconnection patterns on semiconductor integrated circuits, and to reduce discontinuities in the surface or in surface patterns.